Specification Now Available to Member Companies

Cache Coherent Interconnect for Accelerators (CCIX)

Allows multiple processor architectures and accelerators to seamlessly share data 

CCIX is a new chip-to-chip interconnect operating at 25Gbps that allows two or more devices to share data in a cache coherent manner. The standard allows processors based on different instruction set architectures to extend their cache coherency to accelerators, interconnect, and I/O.


These highly capable accelerators become key components in the processor system. CCIX allows system designers the flexibility to choose the right combination of heterogeneous components from multiple vendors and address their specific system needs.


The CCIX standard is now available to member companies allowing designs to start implementing it in future products. Member companies expect to have initial products with CCIX technology in 2017.


Open Acceleration Framework for Data Centers and Other Markets

Accelerating applications in the data center has become a requirement due to power and space constraints. Applications such as big data analytics, search, machine learning, NFV, wireless 4G/5G, in-memory database processing, video analytics, and network processing, benefit from acceleration engines that need to move data seamlessly among the various system components.

Connecting Processor Architecture and Accelerators Seamlessly

CCIX will allow components to access and process data irrespective of where it resides, without the need for complex programming environments. This ability to access data coherently dramatically improves performance and usability by enabling a driver-less and interrupt-less usage model. Additional capabilities include:

  • Both off-load and bump-in-the-wire inline application acceleration while leveraging existing server ecosystems and form-factors
  • Full coherency which allows a complete set of capabilities in the accelerator (home-node, caching-node capability)
  • 25Gbps IO and support for intermediate speeds. Scalable to higher speeds.
  • Builds over PCIe which allows a single interface to be supported in the processor and accelerator.
  • Protocol built for FPGAs, GPUs, network/storage adapters, intelligent networks and any other accelerator


Widespread Collaboration among Industry Technology Leaders

For the first time in the industry, a single interconnect technology specification will ensure that processors using different instruction set architectures (ISA) can coherently share data with accelerators such as GPUs, FPGAs, Smart Network Accelerators, enabling efficient heterogeneous computing and significantly improving compute efficiency for servers running data center workloads.