Cadence Tools and IP Optimized for New Arm Neoverse N1 Platform to Advance the Cloud-to-Edge Infrastructure Market

By Matt Baxter February 20, 2019

  • Cadence DDR4 PHY IP, CCIX IP, and PCIe 4.0 PHY IP integrated and with Neoverse N1 SoC, driving key I/O interfaces to peak levels of performance
  • Arm Neoverse N1 System Design Platform and board based on Neoverse N1 platform and Cadence IP was implemented and verified using Cadence tools in support of CCIX cache coherency for asymmetrical compute acceleration