Xilinx Leads a Tour of Everest

By Matt Baxter August 23, 2018

Xilinx revealed at Hot Chips more details of its plan for a new kind of FPGA targeting the accelerators expected to dominate a post-Moore’s Law era. The architecture, announced in March, includes blocks that can be programmed in high-level languages, but the company has not yet provided enough detail to determine how effective real products will be.

Compared to its current 16nm FPGAs, the so-called Adaptive Compute Acceleration Platform (ACAP) will deliver 20x and 4x performance increases on deep learning and 5G radio processing, respectively, Xilinx claimed. The first chip, called Everest, will tape out this year in a 7nm process.