Presentations
In this presentation at SC19, CCIX Consortium members explain how, through the CCIX interconnect, accelerators can act as co-processors to host, sharing data structures seamlessly with reduced data transfer latency. The presentation discusses two use cases, 1) memory expansion model over CCIX and 2) storage with compute offload, and details the programming model for realizing the potential of CCIX interconnect.
In addition to providing cache coherency, CCIX also allows coherently attached memory expansion, whether volatile or non-volatile. CCIX provides ways for the system to describe to the operating systems’ paged memory to include CCIX device attached memory. By extending the basic premise of existing cache coherent interconnects to accelerators, CCIX enables accelerator memory to be included in the paged system memory available to the application for direct high performance cacheable accesses.
This presentation, presented at Flash Memory Summit 2019 by Ravi Kiran Gummaluri of Xilinx on behalf of the CCIX Consortium, addresses how the CCIX standard enables systems to realize the benefits of increased system memory capacity, power-performance benefits of near-memory processing and inclusion of persistent memory in the system memory pool in applications like Redis and MongoDB.
The CCIX standard cache coherent interface is a high-performance, low-latency chip-to-chip interconnect. The availability of CCIX integrated directly into processors as with Arm’s Neoverse N1 SDP (System Development Platform) enables prototyping of new use cases – one such example being memory expansion and the attachment of Persistent Memory. Through an interface like CCIX, memory can be accessed using byte-addressable and cache coherent load/store semantics – just as if it were DDR-attached DRAM memory. Consequentially, databases for applications such as data analytics and transactions can be hosted completely in the expanded memory leveraging a single shared address space. Persistent Memory can also be more easily attached and scaled. At Lenovo Research, using Arm’s N1 SDP, we’ve investigated the performance of accessing memory attached over CCIX. Results from these efforts will be presented plus applications for Persistent Memory and expanded DRAM capacity will be discussed.
This final webinar in the CCIX member webinar series provides an overview of CCIX Firmware, OS and Management software architecture, starting with the CCIX programming model and the Software-Hardware interface architecture. The webinar also covers CCIX Boot Firmware in a CCIX-based system, CCIX devices discovery and configuration, and Firmware-to-OS interfaces (e.g., UEFI, ACPI).
This webinar is now publicly available on the CCIX YouTube channel.
In the second CCIX member’s webinar, Gord Caruk of AMD provides an overview of the CCIX Transport Layer. Topics include a discussion of features that are leveraged to move CCIX packets, CCIX packet definition, data rate negotiation, and register spaces.
This webinar is now publicly available on the CCIX YouTube channel.
The first in the series of webinars for CCIX members, this webinar provides an overview of CCIX. Millind Mittal of Xilinx Inc. provides an in-depth look at the CCIX architecture framework, key components, and targeted topologies. Bruce Mathewson of Arm continues the session with a discussion on the CCIX Coherency protocol and key coherency concepts, coherency flows, hazard conditions, and mapping the coherency layer to the transport layer.
This webinar is now publicly available on the CCIX YouTube channel.
ArmTechCon17 CCIX A New Coherent Multichip Interconnect for Accelerated Use Cases